A memory system, memory module and memory device are described. The memory system includes a plurality of the memory modules connected in a series configuration on a first signal path. The first signal path and a second signal path carry memory control and data signals between the memory modules and a memory controller. The memory controller transmits and receives the control signals and data signals on the first and second signal paths. The first and second signal paths are connected together such that the memory modules are connected in a ring configuration. The control signals and data signals travel in opposite directions on the first and second signal paths. The first and second signal paths are shared by both the data signals and the control signals. The memory modules include multi-functional ports, each of which can receive both the control signals and the data signals and output the signals onto the connected signal paths. The memory device in accordance with the invention can include multi-functional conductors or pins which can both receive and output both the control signals and the data signals.