A process program such as an erasing/programming program is stored in a boot mat in a nonvolatile memory operational in a boot mode specified after reset start, and a transfer control program for the process program is also stored therein in advance. With an action of setting control information to a predetermined register as trigger, the state of an on-chip CPU is changed from placed in execution of an optional user program to enabled for execution of a transfer control program in the boot mat, and the CPU is returned to the re-execution state of the optional program, after the process program is transferred to an on-chip RAM.

 
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< Management of a memory subsystem

< Generalized queue and specialized register configuration for coordinating communications between tightly coupled processors

> Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration

> Method for interfacing a synchronous memory to an asynchronous memory interface and logic of same
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