A synchronization circuit including a plurality of samplers, the plurality of samplers sampling an input signal with a plurality of respective clock signals and producing a plurality of respective sampled output signals. The synchronization circuit also includes at least one phase detector coupled to the plurality of samplers, the at least one phase detector determining whether the plurality of sampled output signals are different and producing at least one control signal, the at least one control signal indicating whether the plurality of sampled output signals are different. In addition, the synchronization circuit includes a delay adjuster coupled to the at least one phase detector, the delay adjuster adjusting a delay of the input signal according to the at least one control signal output by the at least one phase detector.