In a preferred embodiment, the invention provides a circuit and method for
a high reliability triple redundant latch with integrated testability.
Three settable memory elements set an identical logical value into each
settable memory element. After the settable memory elements are set, a
voting structure with inputs from the second settable memory element, the
third settable memory element and control to the settable memory elements
determine the logical value held on the first settable memory element.
Data may be scanned into and out of the second settable memory element.
Data is propagated through the buffer into the third settable memory
element. The third settable memory element may be used to scan data out
of the triple redundant latch. The propagation delay through a latch is
the only propagation delay of the triple redundant latch.