A demodulator for demodulating S orthogonal modulation codes, each code comprising M binary bits representing an N-bit data symbol, where M=2.sup.N. The demodulator comprises a Logic 00 detector for comparing pairs of binary bits to 00 and outputting [+1,+1] if a match occurs or [-1,-1] otherwise; S accumulators; and a Logic 00 switch array comprising S switches, where a Kth switch couples an output of the Logic 00 detector to a first input of a Kth S accumulator. The demodulator also comprises a storage array for storing S code masks, each code mask comprising M/2 code mask bits and each M/2 code mask bit associated with a corresponding sequential pair of M binary bits; and control circuitry for synchronously applying the M/2 code mask bits in a Kth code mask as a control signal to the Kth switch in the Logic 00 switch array.