An on-chip error correction circuit can be used to correct errors in memory cells of a FPGA. In one embodiment of the invention, the circuit can compute, during configuration, a plurality of error correction bits. These error correction bits are stored in a designated location on the FPGA. After all the memory cells are configured, the error correction circuit continuously computes the error correction bits of the memory cells and compares the result to the corresponding values stored in the designated location. If there is discrepancy, the stored error correction bits are used to correct the errors. In another embodiment of the invention, a plurality of parity bits of the original configuration bits is calculated. These parity bits are stored in registers. The FPGA contains on-chip parity bit generators that generate the corresponding parity bits. A discrepancy between the generated and stored parity triggers error correction action.