A reconfigurable processor circuit (200) consistent with certain embodiments of the present invention has an array of configurable circuit blocks (208), wherein certain of the configurable circuit blocks (208) comprise one of configurable arithmetic logic units and clocked digital logic circuits. A control processor (218) configures a function of a plurality of the configurable circuit blocks. A memory (224) stores program instructions used by the control processor (218). A multiple frequency generator (230) receives a reference clock and synthesizes the plurality of clock signals therefrom, each clock signal being configured in frequency by the control processor (218). A timing control circuit (236) receives the plurality of clock signals, allocates the plurality of clock signals of different frequency among the plurality of circuit blocks and routes the clock signals to the circuit blocks, wherein the timing control circuit (236) operates under control of the control processor (218).