An image processing apparatus enabling alpha blending or other image processing during bit block transfer (bitblt), wherein the selector 52 selects one of the primitive data S143, the image data S12 and the image data S147a that are used for the host-local transfer, and outputs the data to the alpha blend circuit 53. According to the control signal S55, the alpha blend circuit 53 turns on or turns off alpha blending. The selector 54 selects either the image data S139 or the image data S53 and writes the data to the DRAM 147.