A plurality of blocks are optimally placed within a short process time
while minimizing the exceeding of the delay time. Input means receives
information on a logic circuit having a hierarchical structure including
a plurality of blocks, and RTL estimation means calculates a delay time
in the blocks in advance. Path detection means detects a timing path
extending via a plurality of blocks, and delay calculation means
calculates a delay value while assuming that the inter-block interconnect
length is zero. Delay margin setting means sets a delay margin obtained
by subtracting the delay value from a predetermined delay time. The delay
margin forms a part of an objective function as a weight on the virtual
interconnect length between each of the inter-block terminal pairs in the
placement process, and the blocks are automatically placed by using the
objective function.