A data processing system 2 is provided supporting address offset generating instructions which encode bits of an address offset value using previously redundant bits in a legacy instruction encoding whilst maintaining backwards compatibility with that legacy encoding.

 
Web www.patentalert.com

< Option ROM virtualization

< CAM-based search engines and packet coprocessors having results status signaling for completed contexts

> Disk drive executing a preemptive multitasking operating system comprising tasks of varying priority

> Directory-based cache coherency scheme for reducing memory bandwidth loss
~ 00294