A processor supports a processing mode in which the address size is
greater than 32 bits and the operand size may be 32 or 64 bits. The
address size may be nominally indicated as 64 bits, although various
embodiments of the processor may implement any address size which exceeds
32 bits, up to and including 64 bits, in the processing mode. The
processing mode may be established by placing an enable indication in a
control register into an enabled state and by setting a first operating
mode indication and a second operating mode indication in a segment
descriptor to predefined states. Other combinations of the first
operating mode indication and the second operating mode indication may be
used to provide compatibility modes for 32 bit and 16 bit processing
compatible with the x86 processor architecture (with the enable
indication remaining in the enabled state).