A logic verification device, a logic verification method and a logic verification computer program that can reduce the number of steps involved in designing a logic circuit particularly when the designed logic circuit is subjected to logic verification and modification at the spot where an error is detected. The logic verification device comprises a data converter section adapted to convert real circuit data to be processed for designing a logic circuit into data for verification to be processed for logic verification and vice versa, a verifier section adapted to operate for logic verification of said data for verification and a temporary modifier section adapted to acquire the result of verification of said verifier section and the modification candidate data corresponding to the result of verification of said verifier section and pre-selected as candidate data for modification of said data for verification and modify said data for verification on the basis of said acquired result of verification and said acquired modification candidate data.