Techniques for accelerating power estimation for a circuit comprising
generating an RTL description of the circuit. A power model enhanced RTL
description of the circuit is generated. A simulator is selected. The
power model enhanced RTL description is modified to make it more friendly
to the simulator. The simulator is run to estimate the power consumed by
the circuit. Techniques using delayed computation and partitioned
sampling are also provided. Power estimation systems using the above
techniques area also provided.