A semiconductor device fabrication method comprises; a first step S1 of fabricating a plurality of semiconductor chips on a plurality of semiconductor wafers, respectively; a second step S4 of making a probe test on the plural semiconductor chips respectively, which are present in a sampling region of one semiconductor wafer of the plural semiconductor wafers; and the third step S5 of computing a yield of the plural semiconductor chips present in the sampling region, when the yields of the plural semiconductor chips computed in the third step are a reference value or above, the probe test is not made on the plural semiconductor chips, which are present outside the sampling region of said one semiconductor wafer and on the rest semiconductor wafers of the plural semiconductor wafers fabricated in the same lot as said one semiconductor wafer. The probe test is made on the plural semiconductor chips respectively, which are present in the sampling region of said one semiconductor wafer of the plural semiconductor wafers, and when the yield of the semiconductor chips present in the sampling region is the reference value or above, the probe test is not made on the rest semiconductor chips present in the rest region of said one semiconductor wafer other than the sampling region and on the rest semiconductor wafers fabricated in the same lot as said one semiconductor wafer, whereby the inspection period of time can be drastically shortened.