An add-compare-select (ACS) arithmetic unit for a Viterbi decoder is provided. The ACS arithmetic unit includes two 2's complement adders for performing an operation on a state metric related to a bit value 0 and a state metric related to a bit value 1, respectively; a 2's complement subtractor for performing a subtraction on the outputs of the two 2's complement adders; a multiplexer for selecting the smaller output between the outputs of the two 2's complement adders; an absolute value calculator for calculating an absolute value of the subtraction result of the 2's complement subtractor; a look-up table for calculating a log value corresponding to the absolute value generated from the absolute value calculator; and a subtractor for subtracting the log value, which is provided from the look-up table, from the output of the multiplexer to output a state metric Since the ACS arithmetic unit does not need a comparator, a MUX, and a subtractor, which are necessary for normalization, it can use a high system clock signal Consequently, entire throughput can be increased, and latency can be decreased.