A synchronous semiconductor memory device reduces operation current by limiting unnecessary internal operations with a command interval defined in the JEDEC Standard. The synchronous semiconductor memory device comprises a clock buffer, a plurality of command buffers, a plurality of address buffers, a command decoder, a clock driving unit, and a plurality of address latches. Here, the command decoder generates an internal command in response to output signals from the plurality of command buffers synchronously with respect to an internal clock. The clock driving unit drives a clock outputted from the clock buffer to generate the internal clock, and generates a latch clock that toggles only when the internal command is generated. The plurality of address latches generates a plurality of latch addresses in response to a plurality of internal addresses outputted from the plurality of address buffers synchronously with respect to the latch clock.