A design method encompasses: determining a direction of a subject wiring level in a multi-level interconnection of semiconductor integrated circuit as a subject-level priority direction; designing a layout of the subject wiring level, by placing a subject-level strip extending along the subject-level priority; generating a subject-level extension extending in a different direction of the subject-level priority direction, from a termination of the subject-level strip; allocating via-holes in the subject-level extension; and designing a layout of a neighboring wiring level of the subject wiring level, by placing a neighboring-level strip extending along the same direction as the subject-level extension extends, so that a termination of the neighboring-level strip can include the via-holes.

 
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> Substrate independent multiple input bi-directional ESD protection structure

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