Processing circuits that are associated with the operation of threads in an SMT processor can be configured to operate at different performance levels based on a number of threads currently operated by the SMT processor. For example, in some embodiments according to the invention, processing circuits, such as a floating point unit or a data cache, that are associated with the operation of a thread in the SMT processor can operate in one of a high power mode or a low power mode based on the number of threads currently operated by the SMT processor. Furthermore, as the number of threads operated by the SMT operator increases, the performance levels of the processing circuits can be decreased, thereby providing the architectural benefits of the SMT processor while allowing a reduction in the amount of power consumed by the processing circuits associated with the threads. Related computer program products and methods are also disclosed.