An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes a reference current generator (34) for providing a reference current. A first current mirror (46) is coupled to the reference current generator (34) and provides a first predetermined discharge current for discharging the control gate, drain, and source. A second current mirror (36) is coupled to the reference current generator (34) and provides a second predetermined discharge current for discharging the well terminals after the erase operation.