A method and apparatus for analyzing a circuit are described herein. The circuit may comprise at least two nodes, wherein each of the nodes has timing requirements associated therewith. An embodiment of the method comprises receiving a failure time of first node, wherein the failure time represents the time within which a signal must arrive at the first node from the second node in order to avoid a timing violation of the circuit. The second node is upstream of the first node. A potential slack is determined for the first node based on the failure time of the first node, wherein the potential slack is equal to the failure time minus the sum of the target time and the delay between the first node and the second node. The analysis is terminated if the potential slack is less than a first predetermined value. The target slack at the first node is determined, wherein the target slack is equal to the timing requirement of the first node minus the sum of the timing requirement of the second node and the delay between the first node and the second node. The timing requirement of the first node may be changed or relaxed if the target slack is less than a second predetermined value.