A precharge initiated dynamic random access memory (DRAM) technique of especial utility with respect to DRAM devices and other integrated circuit devices incorporating embedded DRAM in which the rising edge of each clock initiates a precharge to those subarrays that were active as opposed to conventional techniques wherein the subarrays are typically precharged so that they are made ready on the rising edge of the clock, which would then start an active cycle. The longer restore time that is achieved can be used to enable the establishment of better logic "1" and "0" levels in the memory cells, to reduce the device clock period and/or to enable other functions to be performed in parallel with the precharge function.