Semiconductor devices are provided on a substrate having a cell array region and a peripheral circuit region. A first device isolation layer defines a cell active region in the cell array region and a second device isolation layer having first and second sidewalls defines a peripheral active region in the peripheral circuit region. A cell gate pattern that includes a plurality of conductive layers crosses over the cell active region, and a peripheral gate pattern that includes a plurality of conductive layers crosses over the peripheral active region. A lowermost layer of the peripheral gate pattern has first and second sidewalls that are aligned with respective of either the first and second sidewalls of the second device isolation layer or a vertical extension of the first and second sidewalls of the second device isolation layer. Further, the lowest layer of the cell gate pattern and the lowest layer of the peripheral gate pattern comprise different conductive layers.