A signal-level converter is provided between a first terminal and a second terminal. The first terminal is connected to a first logic circuit operating at a first supply voltage higher than a given reference voltage. The second terminal is connected to a second logic circuit operating at a second supply voltage higher than the first supply voltage. The signal-level converter has a switching transistor that forms a current passage between the first and the second terminals in response to a control signal supplied to a gate of the switching transistor and a bus-hold circuitry, provided between the switching transistor and either the first or the second terminal as the output terminal, the other being the input terminal, and configured to convert a voltage level of a signal transferred via the switching transistor into another voltage level at the output terminal. The bus-hold circuitry may have two bus-hold circuits between the input and the output terminals, for two-way signal transfer. The bus-hold circuitry may have one bus-hold circuit between the switching transistor and the output terminal, for one-way signal transfer. These circuit arrangements offer reduced chip size and simplified control operations for accurate output-terminal voltages. Moreover, the arrangements omit one direction-switching terminal in two-way signal transfer.