A semiconductor memory device including: a cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of and write data into the cell array; and a controller configured to control read, write and erase of the cell array, wherein the controller executes an erase sequence for erasing a selected block in the cell array in response to erase command and address input in such a way of: executing a first erase-verify operation for verifying an erase state of the selected block; ending the erase sequence if the erase state of the selected block has been verified by the first erase-verify operation; whereas executing an erase operation for the selected block if the erase state has not been verified.