A data detector for use in a communication channel is provided. The data detector includes a path metric unit, which is configured to operate at a rate of at least two samples per clock cycle. The path metric unit includes multiple add units and multiple compare units. In the determination of a lowest path-metric among multiple paths that reach a state, at least one of the multiple add units of the path metric unit operates in parallel with at least one of its multiple compare units, thereby reducing a critical path in the path metric unit.

 
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> Code coverage for an embedded processor system

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