The present invention relates to a method and an universal module for testing functions of communication ports of a computer, including both parallel port and serial port. The module includes a logic control unit and connects to a communication port (a serial or a parallel port) for testing the open or short conditions of the ports through walk 1' and a walk 0' logic tests. The testing module not only can check the open condition of a parallel port, but also can check the open and short conditions of a parallel port and a serial port.