A memory controller system for processing memory access requests comprising a first memory controller operable to address a first plurality of memory modules a second memory controller operable to address a second plurality of memory modules, the first and second memory controllers configurable to process a memory transaction in an operational mode of the memory controller system selected from the group consisting of an independent cell mode, a multiplexer-mode (mux-mode), and a lockstep mode, and a bus interface block operable to convey the memory transaction to both of the first and second memory controllers is provided.