An apparatus for testing a semiconductor device by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, including a silicon wiring substrate on which the chip IPs are mounted. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip-flops to wiring, which are arranged to test connections in the wiring. An IP on Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.