Disclosed are structures and methods that facilitate the use of wire bonding technology over active areas of an IC chip. The invention is also suitable for use with IC structures that use brittle dielectric materials such as low K dielectrics.
Web www.patentalert.com
> Damascene patterning of barrier layer metal for C4 solder bumps
HOME | NEW USER | LOGIN | SUBSCRIPTIONS | SEARCH | GUESTBOOK | CONTACT