The invention concerns an identification method and circuit (1) of the network type of parameters contained in an integrated circuit chip, comprising a single input terminal (2) for applying a signal (E) triggering an identification, the output terminals (3.sub.1, 3.sub.2, 3.sub.i-1, 3.sub.i, 3.sub.n-1, 3.sub.n) adapted to deliver a binary identifying code (B.sub.1, B.sub.2, B.sub.i-1, B.sub.i, B.sub.n-1, B.sub.n), first electrical paths P.sub.1, P.sub.2, P.sub.i, P.sub.n), individually connecting said input terminal to each output terminal, and means (4, 5.sub.1, 5.sub.2, 5.sub.i, 5.sub.n) for simultaneously integrating the binary states present in output of the electrical paths, each path inputting a delay sensitive to technological dispersions and/or of the integrated circuit fabrication method.

 
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> Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing

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