A method of updating a cache in an integrated circuit comprising: the
cache; a processor connected to the cache via a cache bus; a memory
interface connected to the cache via a first bus and to the processor via
a second bus, the first bus being wider than the second bus or the cache
bus; and memory connected to the memory interface via a memory bus; the
method comprising the steps of: (a) following a cache miss, using the
processor to issue a request for first data via a first address, the
first data being that associated with the cache miss; (b) in response to
the request, using the memory interface to fetch the first data from the
memory, and sending the first data to the processor; (c) sending, from
the memory interface and via the first bus, the first data and additional
data, the additional data being that stored in the memory adjacent the
first data; (d) updating the cache with the first data and the additional
data via the first bus; and (e) updating flags in the cache associated
with the first data and the additional data, such that the updated first
data and additional data in the cache is valid.