A plurality of processors share a device using a common PCI bus. Each processor includes a PCI addressable memory area where data sent to or received from the device is stored. Each processor includes a unique identifier and also includes a PCI controller for accessing the PCI bus. Data is sent from a processor to the device by writing the data to the PCI addressable memory area and signaling the device using the processor's unique identifier. The device determines the memory address corresponding to the processor's unique identifier and reads the data. The device sends data to a processor by writing the data to the PCI addressable memory area and signaling the processor using a PCI mailbox assigned to the device and included in the processor's PCI controller. Device parameters are sent by the processors to the device during initialization and the device determines whether a parameter conflict exists.