A system (10) translates memory addresses. Processing circuitry (12) provides an effective address to a storage array (14, 16) having a plurality of stored effective addresses, each of the plurality of stored effective addresses having a corresponding pair of a lock bit and a valid bit. An output tag value and a single valid bit are provided to a comparator (18). The lock bit defines one of two predetermined classes of tasks executed by the system. The single valid bit is applicable to both of the two predetermined classes of tasks. The lock bit qualifies the clearing of the single valid bit. The comparator respectively compares the output tag value and the single valid bit with a predetermined effective address and a predetermined bit value. An output hit signal is provided when a match occurs to validate a physical address provided by a physical address array (20).