The invention relates to a processor system which is configured as a communications controller and which comprises a central processor unit (1) for executing instructions filed in a program memory (8), whereby the processor unit (1) comprises only one path (2,3) for reading out an instruction from the program memory (8) and for decoding the instruction. In addition, several parallelly operable execution paths (4,5;6,7) for parallelly executing different program flows are provided which each access the path (2,3) jointly used for reading out and decoding an instruction.