A timing recovery circuit and related method is disclosed. The timing
recovery circuit encompasses a converter, an interpolator, a phase error
detector, an adjustment circuit, and a calculation circuit. The converter
samples an input signal to generate an intermediate signal carrying
samples of the input signal, while the interpolator inserts an
interpolating sample into the intermediate signal in response to a
control value to generate an output signal. The phase error detector
outputs a phase error of the output signal. The adjustment circuit
updates an over-sampling ratio according to a pair of first and second
thresholds, and a counting value adjusted in response to the phase error
and a median reference value. Finally, the calculation circuit derives
the control value from the updated over-sampling ratio, and transferring
the control value to the interpolator.