A non-volatile memory device and a fabrication method thereof, wherein a charge trapping layer, which is a memory unit, is formed at opposite ends of a gate of a cell, i.e., adjacent to source and drain junction regions, such that portions of the charge trapping layer adjacent to the source and drain junction regions are formed to be thicker than other portions of the charge trapping layer. Therefore, regions adjacent to junction regions function as electron storage regions and hole filing regions.

 
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> Transistor mobility improvement by adjusting stress in shallow trench isolation

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