A method for performing layout verification involves identifying feature centerlines in a mask layout, and then performing lithography simulation along the centerlines to generate a set of intensity distributions. At each local maxima or minima in the intensity distributions, further lithography simulation can be performed to determine an exposure pattern width at those local maxima/minima (check positions). The exposure pattern widths can then be evaluated to determine whether an actual pinch or bridge defect will be generated at those locations. If defect generation is likely (based on the lithographical simulation) at a particular location, the corresponding portion of the mask layout can be redesigned to avoid defect generation during actual production. In this method, accurate layout verification can be performed with a minimum of time-consuming lithography modeling.