A plurality of processors on a chip is operated in lockstep. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache. As data is stored in a first bank of the L2 cache, the old data at that location is passed through the crossbar switch to a second bank of the L2 cache that is functioning as a first-in-first-out memory (FIFO). Thus, new data is cached at a location in the first bank of the level-two cache, i.e., stored, and old data, from that location, is logged in the second bank of the level-two cache. The logged data in the second bank is used to restore the first bank to a known prior state when necessary.