An ASIC that includes a data latch for latching a data signal from a CPU and a buffer for holding the data signal output from the latch. When presently latched signal is at a higher electric potential than the data signal outputted to the buffer, that is, when then the data signal from the CPU changes from an H state to an L state, then the ASIC delays output of the buffered data signal to a memory (a pair of DIMMs) for one or more periods of the synchronization clock.