An interpolation circuit (10) generates a plurality of intermediate amplitude values linearly related to two consecutive signal amplitude values using a system of adders and memory elements. A first stage (64) of the interpolation circuit calculates a one-half amplitude value; a second stage (66) calculates one-fourth and three-fourths amplitude values, and a third stage (68) calculates one-eighth, three-eighths, five-eighths, and seven-eighths amplitude values. A comparator (14) receives a threshold value (32) and compares each of the intermediate amplitude values to the threshold value. A decoder (16) generates a time of arrival adjustment value that is subtracted from a low resolution time of arrival to generate a high resolution time of arrival.