A single integrated circuit (12). The integrated circuit comprises a first circuit (14.sub.x) having a data path, the first circuit consisting of a first number of logic gates for performing a plurality of logic functions. The integrated circuit also comprises a circuit (22.sub.x) for indicating a potential speed capability of the data path. The circuit for indicating comprises a second number of logic gates (82, 92) for performing the plurality of logic functions, wherein the second number is less than the first number. The circuit for indicating also comprises additional circuitry (88, 98) for representing parasitic characteristics in the data path.

 
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> Apparatus and method for invalidation of redundant branch target address cache entries

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