In one embodiment, a method for layout-driven, area-constrained design optimization includes accessing a design and a layout of the design. The design includes one or more gates and one or more nets coupling the gates to each other. The layout includes blocks that partition a chip area of the design. Each block includes one or more of the gates. The layout also includes a global routing of the nets. The method also includes performing a first timing analysis of the design and the layout and updating the design and the layout. The method also includes performing a second timing analysis of the design and the layout. The second timing analysis takes into account the updates to the design and the layout. The method also includes, if one or more results of the second timing analysis indicate that the design does not meet one or more predetermined design goals and indicate at least a predetermined amount of progress toward one or more of the design goals relative to the one or more results of the first timing analysis, further updating the design and the layout.