A device for verifying hardware in a circuit arrangement that includes one or more configuration elements (106) operable to configure hardware elements (108) that are electrically coupled by one or more electrically-conductive pathways (110). The device includes a hardware-verification register (202) coupled to at least one of the electrically-conductive pathways (110). The register (202) is operable to sample a voltage level on at least one of the electrically-conductive pathways (110) at a first time point; store in a memory one or more bits, each bit representing the voltage level on at least one of the electrically-conductive pathways (110) at the first time point; sample a voltage level on at least one of the electrically-conductive pathways (110) at a second time point; and compare, for at least one of the electrically-conductive pathways, the voltage level at the first time point and the voltage level at the second time point.