A high availability packet forwarding router for an internet protocol (IP) network, includes two control processors, one or more service termination cards (STCs) with forwarding information bases (FIBs), and a packet forwarding engine. The two processors run asynchronously in a master/standby relationship. Integrity of processes running on the control processors is monitored and the forwarding engine forwards packets according to a FIB maintained by an in-service one of the control processors. Hitless failover and hitless software upgrades are supported.