A controller device and method for operating same is disclosed. In one particular exemplary embodiment, the controller device may comprise output driver circuitry and input receiver circuitry. The output driver circuitry may output a value, a first operation code, a block size value, and second operation code. The first operation code may represent an instruction to a memory device to store the value in a register in the memory device. The block size value may indicate an amount of read data to be output by the memory device in response to the second operation code. The second operation code may represent an instruction to the memory device to perform a read operation. The input receiver circuitry may sample a first portion of the read data output by the memory device after a read delay following the outputting of the second operation code.