The present invention provides a system and method for implementing postponed quasi-masking test output compression in an integrated circuit. The system includes a compressor for compressing a test response from N scan chains of an integrated circuit into M outputs. The test response may indicate faults in the integrated circuit. M and N are positive integers. The system further includes a correctable multiple input signature register with a size of M, which is communicatively coupled to the compressor. The correctable multiple input signature register is suitable for receiving the M outputs from the compressor as data inputs (s[0], . . . , s[M-1]) and receiving M correction bits (c[0], . . . , c[M-1]) and L address bits (a[0], . . . , a[L-1]) as correction inputs, L being a positive integer, 2.sup.L>=M. The correctable multiple input signature register is suitable for detecting faults when there is no or at least one unknown value (i.e., X-value) in the test response.

 
Web www.patentalert.com

> Integrated system logic and ABIST data compression for an SRAM directory

~ 00343