An input processing circuit is interposed between input terminals and input ports of an MPU. An output processing circuit is interposed between output ports of the MPU and output terminals. The input processing circuit includes switch sections and processing sections. The output processing circuit includes switch sections and processing sections. A switch control section switches the switch sections based on switch information stored in a switch information storage section to switch a connection relationship between the input terminals and the input ports, processing for an input signal, a connection relationship between the output ports and the output terminals, and processing for an output signal.