A method of HDL simulation is described, which may enhance HDL simulation
accuracy by allowing a simulator to process a negative setup time and/or
hold time. For an electronic circuit device negative setup time and/or a
negative hold time, a simulation may be executed without altering the
negative setup time and/or hold time to be interpreted as zero. A setup
time and/or hold time may be negative relative to a particular clock
cycle while being positive relative to another clock cycle. Incorporating
the value of the negative setup time and/or hold time without altering
its value to zero may increase the accuracy of HDL simulations.