A chip-type solid electrolytic capacitor has a four-terminal structure. The chip-type solid electrolytic capacitor includes capacitor elements laminated such that anode electrodes face alternately in opposite directions; a pair of anode terminals opposing each other; and a pair of cathode terminals opposing each other. The magnetic fluxes generated by current passing between respective terminals are mutually cancelled, thus allowing ESL to be drastically reduced. Further reduction of ESL is feasible by shortening the distance between the terminals as much as possible so as to reduce the current loop area.

 
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> Synthetic pattern exchange configuration for side reading reduction

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