A low dropout voltage (LDO) regulator comprises an output stage (EtS) of the amplifier (AMP), which has a main output and n auxiliary outputs which can respectively deliver a main control voltage (V.sub.GPRINC) and n auxiliary control voltages (V.sub.G1, . . . , V.sub.Gn); and a power stage (EtP) which has a main power transistor (PmosPrinc), controlled at its gate by the main control voltage (V.sub.GPRINC), and p power modules (module 1, . . . , module n) of identical layout with p less than or equal to n, respectively having p auxiliary power transistors (PMos1, . . . , PMosn) each controlled at their gate by p auxiliary control voltages (V.sub.G1, . . . , V.sub.Gn). The number p is selected as a function of an intended maximum output current.